What's the ice40 clock speed on the sdk board?

[r.miller]

On the schematic, pin 129 is labelled 100M. In the verilog sdk/src/spi_pwm.v, a comment for the clk signal says "100MHz clock input".

In the pin configuration file sdk/src/mystorm.pcf, a comment for clk/129 says "Onboard 12Mhz oscillator".

When I route the clk signal to a PI_GPIO pin with a verilog assign, my oscilloscope tells me that it's ticking at 33.33 MHz. Looking at Olimex pin 6 also confirms 33.33 MHz.

I'm confused!

[dsilvers]

My RR SDK board has an osc labelled 100.00

If you look in the corner of the placed area next to the FPGA's top-side, the oscillator should have a speed labelled on it.

[r.miller]

My RR SDK board has an osc labelled 100.00

Mine too -- that's part of the reason I'm confused. In case I was mis-reading the scope, I've also tried blinking an ice40 LED at 1Hz by dividing the clk signal by 33333333, and that seems to keep pace with my wristwatch.

[Folknology]

The FPGA oscilator is 100Mhz

[Folknology]

Have you checked the oscillator output directly?

[r.miller]

Have you checked the oscillator output directly?

On the component labelled HX0-36B, the pin nearest the ice40 reads 33.33 Mhz (period is 30.0 ns). The voltage cycles from -1.0V to 3.75V.

[Folknology]

That is very strange the only thing I can think of is that a wrong oscillator has been installed..

[r.miller]

Here's my theory: the 100MHz oscillator has a 33.33MHz crystal which is meant to vibrate at the third harmonic. Somehow during my tinkering with the board, the crystal or its supporting circuitry has been damaged so that it now vibrates at the fundamental frequency instead.

Not a show stopper -- I can use a PLL on the ice40 to generate a 100MHz clock from the slower input clock.