@folknology If the main language for programming the Alloy fpga is to be nmigen, I was wondering how we would access the RAM. The BRAM is no problem an nmigen supports that using
Memory.(...). But i don't think it has support for the 128kb of single-port ram (SPRAM) on the up5k.
The only way i have used that is through @daveshah's code that use the Lattice primitive's - https://github.com/daveshah1/picorv32/blob/up5k/picosoc/up_spram.v, but I am not sure how you would use that from nmigen.
The discussion that I have seen on using SPRAM from nmigen was rather old, so perhaps there is a way of doing it now.
If there was a simple way of incorporating Verilog modules from nmigen programs (like the SpinalHDL Blackbox), then we could use that, but I have not seen any such facility. Do you know of a way of doing that?
The other type of ram that I believe you are going to have on Alloy is SPI RAM. Presumably, we will have to write a controller for that. I guess it will be similar to an SPI flash memory controller.