Tile and Stack expansion idea

[Folknology]

Update on all things myStorm - streaming

12 FPGA pins seems rather few to go to a tile, as you cannot do the equivalent of a double Pmod with it, as that needs 16 pins.

For example the Digilent VGA Pmod with 4 bits per colour needs 14 FPGA pins, so we wouldn't be able to do the equivalent of that.

The pins are not yet set in stone but in response:
1. The planned Amalgam Stack could also accept that Pmod (it has a single mixmod/double pmod built in also)
2. I would prefer to do a retro board with VGA, USB and game controllers so would make it a double Tile myself which would have plenty of IOs

But it is a great idea to try to think of peripherals that are challenged by the current proposed number of IOs, as many as we can please, that way we can make this the best possible solution..

[Folknology]

Current design for tiles (incl 26 pin 2x rows of 13 x 0.1" header):

F12-F15 are dedicated SPI
The main board (FPGA side) has a female connector, the Tile itself will have a male header and could be SMD or through hole.

[lawrie]

But it is a great idea to try to think of peripherals that are challenged by the current proposed number of IOs, as many as we can please, that way we can make this the best possible solution..

I don't often use double Pmods other than the VGA one, but I have some which might not work with a single tile and 12 FPGA pins:

• OV7670 camera
• LED Panel
• 1bitsquared HDMI Pmod
• 1bitsquared Hyperram Pmod

[Folknology]

OV7670 camera
LED Panel

These can be handled on a single Tile 12 FPGA signals, especially when combined with the I2C and over GPIO

[Folknology]

1bitsquared HDMI Pmod
1bitsquared Hyperram Pmod

This is more tricky, but on the Amalgam you would have DDRAM anyhow along with a HDMI connector. To do a decent HDMI 24 pins (double Tile) would be more reasonable anyhow IMHO.

For HyperRam you only need 11 FPGA pins I think:
IO0-IO7, CS, CLK & DQS
(with CS0 & CS1 a tile could have 2 HyperRams)
There are 1.8V modes which may require a diff clock in which case single HyperRam on a tile

[Folknology]

I am considering loosing the USB host connector on BIV then I can use Ice40 pins to do the SPi pins, which actually means there are 13 FPGA pins if you don't use spi..

[lawrie]

If the main purpose of BIV is to test the tile concept before making the Ecp5 boards, I would keep it as simple as possible and only put on it things that will be on the ECP5 boards and which you want to test.