As DDR isn't so easy to use, is there a DDR controller within the open source tool chain? How wide might the DDR be? 32 bits would be good!
For the on-chip RAM, I found a table here, which says LFE5U-12 has 32 blocks of 18kbit RAM, which gives 64k bytes, and LFE5U-45 has 108 blocks, which gives 216k bytes. These block RAMs seem to be variously described as sysMEM, EBR and Embedded Block RAM.
For calibration, an Acorn BBC Master 128 with a filesystem ROM and a 64k second processor with a small boot ROM would pretty much use all the on-chip RAM. Or to put it more positively, the ECP5 45k chip is big enough to contain that whole system.