So I think I have found a bug in the HAL QSPI stuff, this is from using dummy cycles in HAL_QSPI_Transmit(), it works fine in HAL_QSPI_Receive().
First an image from the HAL QSPI documentation:
So everything is being done on spi clk fall.
Now an Image from my snazzy new logic analyser:
The top shows a decoder for SPI, then a parallel bus, this bus has the bytes that my qspi is receiving triggered by rxReady ! rxHalfReady.
The STM is sending Command 0x01, 16 bit address of 0x0000, 4 cycles dummy and then 4 integers 0,1,2,3
The STM is driving io1 high and io0 low during the dummy cycles, the issue is the io1 is falling half of a spi clock cycle too late on the rising edge and this is messing up the next bit read.
When using HAL_QSPI_Receive() io1 falls half of an spi clock early, which is still wrong but not as damaging!