So I have implemented in SpinalHDL some basic code which is basically using the SPI library code that they provide and a simple state machine.
This basically samples the SPI clock with the fabric clock and drives everything with the sampled clock, so this needs a much higher fabric clock than the SPI clock. To make things worse the HAL QSPI code is sampling the returned data on the rise of the SPI clock, so my state changes eat up time requiring an even higher fabric clock.
I have been thinking a bit about this and it doesn't seem the most efficient way of doing things, but I'm not much of a programable logic guy so I thought I would run over an idea to see what you guys think:
If part of the SPI slave worked instead directly on the SPI clock to serialise/deserialise the data and then flag a READY state that a byte is available, the rest of the logic only needs work off of this flag, so can run at a much slower clock rate than the previous implementation.
So the other part of the logic uses a little state machine:
write next byte
read last byte
goto WAIT state
if !READY goto TX/RX State
Does this seem like a runner?