Hi,
I think I have run into a weird problem and I don't know if this is specifically to do with the toolchain or with the Verilog I have written or with something entirely else. Let me explain my problem. Please point me in the right direction if this is the wrong forum to ask such a query.
So, I am interfacing an LCD with the myStorm board via the PMOD GPIOs. It is part of the EDSAC FPGA Museum project I am doing. The LCD will show the current values held in the various registers (registers is not how the designers referred to it but it is pretty much that).
I have written an FSM that is supposed to sent instructions to the LCD sequentially. The Verilog looks something like this,
module lcd ( ... );
parameter lcd_cmd = ... ;
delay dl (delay_start, delay_done, clk);
// The clock here is coming from a clock divider and is thus at a lower
// frequency than the onboard 100MHz clock.
always @(posedge clk) begin
case (state)
0: begin
// en is a pulse whose negative edge
// causes LCD to latch onto command or data.
en <= 1;
...
delay_start <=1; // Starts delay
end
...
endcase
end
// Positive edge of delay_done indicates
// count has rolled over, so en is lowered.
always @(posedge delay_done) begin
en <= 0;
end
endmodule
module delay (input delay_start, output delay_done, input clk);
/* As long as delay_start is high, keeps counting. When counter
* rolls over, positive edge is emitted as delay_done.
*/
endmodule
I wrote a testbench for this and simulated it using iverilog and gtkwave. The simulation turns out just as expected. But when I program it onto the myStorm board using the standard make commands with yosys, arachne-pnr and icepack, it does not work as expected. So I debugged the Verilog by hooking up onboard LEDs to various signal changes I thought were responsible for failure. It turns out that posedge delay_done was never being triggered.
This issue was resolved by using always @(posedge clk_d) where clk_d is coming from another clock divider and is at a frequency in between the clk above and100 MHz. It seems that edge triggers occur only for clk or clk-derived signals.
Could someone please explain why this is happening? The simulation runs perfectly as expected on the original code. However, the modified program seems to work on the myStorm board (I can say so because the debug mechanism with onboard LEDs was functioning as expected). What is this issue related to? Any info on it is appreciated.
I'd be glad to explain my problem even more if you'd like. Thank you.
Regards,
Hatim
