SDRAM controllers are hard, particularly on ice40 with icestorm.
My next issue is that I need a phase delay (of possibly about 3ns) between the FPGA clock and the SDRAM clock.
I think I need an SB_PLL40_2F_CORE pll, something like:
) pll2 (
.REFERENCECLK (clk_25mhz ),
.PLLOUTGLOBALA (clk ),
.PLLOUTGLOBALB (sdRamClk ),
.LOCK (pll2_locked ),
.BYPASS (1'b0 ),
.RESETB (1'b1 )
But I probably need help in getting the parameters right for that.
The next issue is that the SDRAM controller needs flip-flops in the IO pads to work at any reasonable speed (like @TomV did for the optimised SRAM Controller).
But the SpinalHDL version does not have that as most proprietary software infers that a register needs to be a FF in the IO pad. So I need a custom version of the SpinalHDL SDRAM controller.
Charles Papon (Dolu1990) is currently working on a DDR SDRAM controller, which will be needed for the Blackedge board. That is much harder, still.