RP2040 PIO FPGA implementation

lawrie 2021-01-30 19:21:25 UTC #1

I have started a Verilog implementation of PIO - https://github.com/lawrie/fpga_pio/tree/main/src

Currently it just runs in simulation and is a long way from working, but most of the structure is there.

Run make sim in the src directory to run the simulation and produce a vcd file.

Folknology 2021-01-30 20:59:58 UTC #2

Nice work Lawrie, bit different from our stream version, let me have a play with the sim. BTW my Pico arrived today, so I can start some comparisons and tests, did you get yours yet?

Folknology 2021-01-30 22:41:11 UTC #3

BTW I also started on the nMigen version earlier, we may need to compare notes/namimg etc..

lawrie 2021-01-30 22:51:10 UTC #4

I just added a bit more, but still a long way from working.

There is a lot in the PIO spec and despite the excellent documentation, not all of it is that easy to understand.

My Pico has also arrived, but I have not used it yet.

Folknology 2021-01-30 23:21:55 UTC #5

Why use "stalled" rather than "wait' inside program counter?
I think they use stalled as a term when the fifo is empty for example

lawrie 2021-01-30 23:36:33 UTC #6

3.2.4. Stalling
State machines may momentarily pause execution for a number of reasons:
• A WAIT instruction’s condition is not yet met
• A blocking PULL when the TX FIFO is empty, or a blocking PUSH when the RX FIFO is full
• An IRQ WAIT instruction which has set an IRQ flag, and is waiting for it to clear
• An OUT instruction when autopull is enabled, OSR has reached its shift threshold, and the TX FIFO is empty
• An IN instruction when autopush is enabled, ISR reaches its shift threshold, and the RX FIFO is full
In this case, the program counter does not advance, and the state machine will continue executing this instruction on the
next cycle. If the instruction specifies some number of delay cycles before the next instruction starts, these do not begin
until after the stall clears.

It seemed the right term from that.

Folknology 2021-01-30 23:58:15 UTC #7

Hmm maybe "waiting' in machine should be changed to "stalled" also then

lawrie 2021-01-31 00:00:23 UTC #8

Possibly. I haven't written much of the code for the various stalled conditions yet.

Folknology 2021-01-31 00:05:17 UTC #9

I was using "pause" just to make things really confusing

lawrie 2021-01-31 01:04:32 UTC #10

My simulation is now running the square wave program (sort of), with a few hacks.

lawrie 2021-01-31 09:55:58 UTC #11

I changed pclk to a clock enable signal (penable), as it makes doing the undivided clock easier, makes reset easier, and is better for synthesis.

Folknology 2021-01-31 12:55:27 UTC #12

I have been avoiding the Fifos due to complexities of implementation, I see you have made a simple one. I want to use the tried and tested nMigen library classes which support a standard interface along with sync/async and buffered selections. Some can use Blockram and others not but using the library Fifos allows interchangeability (allowing for clock domain crossing for example).

lawrie 2021-01-31 13:03:24 UTC #13

My Fifos are not working yet. I will need a suitable example to test them.

I suspect the simple Fifos will be good enough for PIO, but if you want to evolve it into something else, the nmigen fifos will give you more oprtions.

Folknology 2021-01-31 13:19:29 UTC #14

I'm going through your overnight changes, I might just use the simple fifo for now.

lawrie 2021-01-31 13:27:49 UTC #15

The changes are still coming. I have not done shifts yet.

BigEd 2021-01-31 14:45:52 UTC #16

Just to say, excellent project and great to see blow-by-blow progress.

lawrie 2021-02-01 17:07:29 UTC #17

The uart implementation is now more or less working in my version. You can send data from the test bench, through the fifo, and the output shifter to implement the uart protocol on a TX pin. The x scratch register is used to count out the bits. The program is only 4 instructions. There are a few variants of it in RP2040 documentation.

github.com

lawrie/fpga_pio/blob/main/src/tb.v#L26-L34


// Configuration
// uart program
reg [15:0] program [0:31];
initial begin
  program[0] = 16'b100_11000_101_00000; // pull side 1
  program[1] = 16'b111_10111_001_00111; // set x 7, side 0 [7]
  program[2] = 16'b011_00000_000_00001; // out pins 1
  program[3] = 16'b000_00110_010_00010; // jmp x-- 2 [6]
end

The pull instruction waits for data (a byte) from the fifo, and sets TX high while this is happening.
When it arrives the data is put in the output shift register.
The set, sets X to 7 and implements the start bit - 8 cycles of zero.
The out instruction shifts out bits to the TX pin, one bit at a time.
The jump instruction, decrements X and jumps to the OUT instruction if X is not zero.
When X is zero, the program wraps round and starts again with a pull for the next byte.
The version in the micropython SDK adds a NOP with a side set and delay, to implement the stop bit.

You can configure a clock divider to set the baud rate. The frequency needs to be 8 times the baud rate.

lawrie 2021-02-05 09:32:03 UTC #18

A blinky is now working on the Blackice MX:

github.com

lawrie/fpga_pio/blob/main/src/top/top.v

`default_nettype none
module top (
  input         clk_25mhz,
  // Buttons
  input [6:0]   btn,
  // Leds
  output [7:0]  led,
  output [27:0] gn,
  output        tx
);

  // PIO registers and wires
  reg [31:0]  din;        // Data sent to PIO
  reg [4:0]   index;      // Instruction index
  reg [3:0]   action;     // Action to be done by PIO
  reg [1:0]   mindex;     // Machine index
  reg [31:0]  gpio_in;    // Input pins to PIO

  wire [31:0] gpio_out;   // Output pins from PIO
  wire [31:0] gpio_dir;   // Pin directions

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lawrie 2021-02-18 11:27:54 UTC #19

Following on from last night's stream, here is a more sophisticated version of the PIO program driving a stepper motor on a Raspberry Pi Pico:

And here is the micropython version of the program:

github.com

lawrie/fpga_pio/blob/main/pio_stepper.py

import time
import rp2
from machine import Pin

@rp2.asm_pio(out_init=(rp2.PIO.OUT_LOW,rp2.PIO.OUT_LOW,rp2.PIO.OUT_LOW,rp2.PIO.OUT_LOW))
def stepper():
    pull()
    mov(isr, osr)
    pull()
    mov(y, osr)
    label("outer")
    mov(osr, isr)
    set(x, 6)
    label("inner")
    out(pins, 4) [1]
    jmp(x_dec, "inner")
    out(pins, 4)
    jmp(y_dec, "outer")
    wrap_target()
    out(pins, 4)

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I have not tried the program using my Verilog version of PIO on a Blackice MX yet, but I believe it should work.

Folknology 2021-02-18 12:06:38 UTC #20

Do it, do it!