Thanks Lawrie that might be a step in the right direction. Yes indeed it does take much longer to build when these variables are connected. And you are right: I am using some arrays in this part of the code so maybe I'll explain a bit more explicitly what this part of the project does.
- reads a look up table (array) by an index produced in some math in module 2.
(This is where it breaks down, if I do not update this index based on the input, but instead based on the modules own internal counter, the two modules successfully build).
- produces initial timing (counter) for the things happening in module 2
- generates i2s clocking and data for a DAC.
- intakes the timing (counter) generated in Module 1
-reads other arrays using that counter as index
-does math on the outputs of these arrays
-writes these modified values to a "dynamic array" which is being rewritten to on each clock count.
-outputs array[index] through a bus back to Module 1. (this value serves as an index for the lookup table in module 1, which breaks down when I connect it up).
-also outputs these array[index] values to an LCD driver module for display. (at a different clock rate, I should point out)
Does this point you more at what might be the problem? I'll build again with and without the connection and see what it says about BRAM. Is there something I can can specify to yosys about this?