I've been working with BigEd to try to port the OPC-6 System to BlackIce. OPC is our one-page computing effort, more details of which can be found here:
When we added the external SRAM to the project, we hit the following arachne error:
failed to place: placed 0 PLLs of 1 / 2
It would appear that using a PLL can constrain the the use of adjacent IO pins to be output only,
There is some information on these constraints on page 17 of the PLL design guide here:
PLL Placement Rules
- If any instance of PLL is placed in the location of the IO cell, then, an instance of SB_GB_IO cannot be placed in that particular IO cell.
- If an instance of ice40_PLL_CORE or ice40_PLL_2F_CORE is placed, an instance of SB_IO in “output-only” mode can be placed in the associated IO cell location.
- If an instance of ice40_PLL_PAD, ice40_PLL_2F_PAD, ice40_PLL_2_PAD is placed, the associated IO cell cannot be used by any SB_IO or SB_GB_IO.
- If an instance of ice40_PLL_2F_CORE, ice40_PLL_2F_PAD, ice40_PLL_2_PAD is placed, an instance of SB_IO in “output-only” mode can be placed in the right neighboring IO cell.
And also here, right at the bottom:
The PLL clock outputs are fed directly into the input path of certain IO tiles. In case of the 1k chip the PORTA clock is fed into PIO 1 of IO Tile (6 0) and the PORTB clock is fed into PIO 0 of IO Tile (7 0). Because of this, those two PIOs can only be used as output Pins by the FPGA fabric when the PLL ports are being used.
I'm starting to suspect that on BlackIce the FPGA pin assignment of the external RAM data bus is such that it's not possible to use either of the PLLs, which would be unfortunate.
Is this an issue that anyone else has worked through?