Exciting news: seems that open-source FPGA tools now support Lattice's (larger) ECP5 FPGAs well enough that David Shah reports bringing up a Linux on the open source CPU mor1k (Open RISC 1000 architecture).
I think it turned out a new router was needed.
Upcoming talk on Dec 3rd:
Project Trellis enables a fully open-source flow for ECP5 FPGAs using Yosys for Verilog synthesis and nextpnr for place and route. Project Trellis itself provides the device database and tools for bitstream creation.
and see mor1kx on github: