This is an interesting idea, I was just thinking how this could be implemented, Lattice quotes :
If Cold Boot is enabled, the FPGA reads the logic values on pins CBSEL[1:0]. The FPGA uses the value as a vector and then reads from the indicated vector address.
Given that I can control CBSEL[1:0] from the STM32 it could offer a menu to select which vector. However I could only change CBSEL1 in practice as this is connected to wp on the flash, the other is connected to the hold pin which would mess with loading from the flash if enabled..
It might be possible to overcome this by monitoring the Ice40 SS pin and releasing hold when it changes or after a fixed time from Ice40 reset perhaps.
Actually we could only fit 3 full images in the 4Mbit flash, also one is likely to require some runtime flash in addition to Ice40 bit images so maybe limiting it to fewer choices makes more sense, 2 choices is perhaps best..