Magic clk 60 represents pin number or 25 MHz speed?

[Aclassifier]

I'll start my venture with this new Verilog category with a very basic question which I still have not been able to resolve other by trying to infer.

I have not been able to find out where 60 is supposed to map to 25 MHz? Or is 60 the pin number on the iCE40 FPGA where MCLK seems to come from the STM32 uC?

In the MHz direction: I have looked in the iCE40 data (iCE40 LP/HX Family Data Sheet FPGA-DS-02029-3.5 September 2018) and searched for clk, clock, MHz, 60 and 25 with no luck. Also, I found nothing with nextpnr documents (https://github.com/YosysHQ/nextpnr) that solved my question.

And how does Verilog know that the first param here is a clock? If it is speed I could understand it, if it stands for pin number (most likely) then it must be the only pin that Verilog sees (no it doesn't see it..). Or maybe module is inputted to yoysys that outputs the blif file with this stuff in, that arachne-pnr takes and uses the value 60 for. Because I don't' think yosys sees the pcf file with the value 60 at all. So the module definition is just an abstract interface? So my name clk_25MHz would be rather confusing (I did pick it up somewhere). Maybe the name should be clk_abstract_io_pin?

module chip (
    // 25Hz clock input
    input clk_25MHz,
    // led outputs
    output [9:0] led,
);

trail my_trail (
    .clk_25MHz (clk_25MHz),
    .leds (led[9:0])
);

It's 60 for arachne-pnr, but what is is for nextpnr? I assume 60, since I am more and more convinced that it's the pin number. Starting to look at nextpnr now.

And the FPGA clock is 100 MHz. Which SW knows that?

[Folknology]

I have not been able to find out where 60 is supposed to map to 25 MHz? Or is 60 the pin number on the iCE40 FPGA where MCLK seems to come from the STM32 uC?

60 is the pin number of the Ice40 144pin package in the PCF file for the clk signal input just in the same way any other IO pin is specified in a PCF file it isn't special.

The clock signal itself is generated by the STM32 and output through MCO output pin and connected to pin 60 on the Ice40. The clock frequency that is output is 25Mhz, this could be changed in the STM32 firmware if one required it, However it is normally better to route it to one of the PLLs in the Ice40 and have that generate the frequency you require.

And how does Verilog know that the first param here is a clock? If it is speed I could understand it, if it stands for pin number (most likely) then it must be the only pin that Verilog sees (no it doesn't see it..). Or maybe module is inputted to yoysys that outputs the blif file with this stuff in, that arachne-pnr takes and uses the value 60 for. Because I don't' think yosys sees the pcf file with the value 60 at all. So the module definition is just an abstract interface? So my name clk_25MHz would be rather confusing (I did pick it up somewhere). Maybe the name should be clk_abstract_io_pin?

The Verilog knows nothing of the frequency of the clock, it merely 'behaves' on the signal's positive edge. There is no insider information here.

[Aclassifier]

Thanks, @Folknology. I do know that I ask questions that have obvious answers, when one knows them, and I do know that some questions are stupid, but that depends on the receivers too. This forum just lifts me up. Even when i slightly seem to repeat myself. Thanks!

However it is normally better to route it to one of the PLLs in the Ice40 and have that generate the frequency you require.

So 25 MHz goes to pin 60 and an internal PLL may take it up to 100 MHz (what's max?)?

However, the makefile I use I think that there is no PLL upscaling, that clk is indeed 25 MHz. I learnt that in Blink example, clk frequency and blinking rate.

However, a pin 129 (CLK) that to me seems to be a clock output that is used by the SDRAM pin 35 as discussed in What’s the ice40 clock speed on the sdk board? (by @r.miller) that points to gitlab ../src/mystorm.pcf). But there it looks like pin 129 is a clk input (but I think that's on the previous board). I see that @r.miller here suggest to scale the 25 MHz up in an internal PLL to 100 MHz. How would one scale up to, like 100 MHz? I guess there would be params to the PLL that's not Verilog?

Also, what's the speed of the STM32's two crystals?

[r.miller]

How would one scale up to, like 100 MHz? I guess there would be params to the PLL that's not Verilog?

Use the icepll command from the icestorm suite, for example:

icepll -i 25 -o 100 -m -f pll.v

generates this verilog in file pll.v:

module pll(
	input  clock_in,
	output clock_out,
	output locked
	);

SB_PLL40_CORE #(
		.FEEDBACK_PATH("SIMPLE"),
		.DIVR(4'b0000),		// DIVR =  0
		.DIVF(7'b0011111),	// DIVF = 31
		.DIVQ(3'b011),		// DIVQ =  3
		.FILTER_RANGE(3'b010)	// FILTER_RANGE = 2
	) uut (
		.LOCK(locked),
		.RESETB(1'b1),
		.BYPASS(1'b0),
		.REFERENCECLK(clock_in),
		.PLLOUTCORE(clock_out)
		);

endmodule

[r.miller]

So 25 MHz goes to pin 60 and an internal PLL may take it up to 100 MHz (what's max?)?

275 MHz according to the Ice40 LP/HX family data sheet.

[Aclassifier]

Magic! Thanks, @r.miller!