I'll start my venture with this new Verilog category with a very basic question which I still have not been able to resolve other by trying to infer.
I have not been able to find out where 60 is supposed to map to 25 MHz? Or is 60 the pin number on the iCE40 FPGA where MCLK seems to come from the STM32 uC?
In the MHz direction: I have looked in the iCE40 data (iCE40 LP/HX Family Data Sheet FPGA-DS-02029-3.5 September 2018) and searched for
25 with no luck. Also, I found nothing with nextpnr documents (https://github.com/YosysHQ/nextpnr) that solved my question.
And how does Verilog know that the first param here is a clock? If it is speed I could understand it, if it stands for pin number (most likely) then it must be the only pin that Verilog sees (no it doesn't see it..). Or maybe module is inputted to yoysys that outputs the blif file with this stuff in, that arachne-pnr takes and uses the value 60 for. Because I don't' think yosys sees the pcf file with the value 60 at all. So the module definition is just an abstract interface? So my name
clk_25MHz would be rather confusing (I did pick it up somewhere). Maybe the name should be
module chip (
// 25Hz clock input
// led outputs
output [9:0] led,
trail my_trail (
It's 60 for arachne-pnr, but what is is for nextpnr? I assume 60, since I am more and more convinced that it's the pin number. Starting to look at nextpnr now.
And the FPGA clock is 100 MHz. Which SW knows that?