IceTea is a peripheral for the TI-99/4A home computer, based on BlackIce. It will provide paged RAM, I/O devices, and especially a new sound synthesizer for the FORTi music software (Texas Peripherals, 1984) written in TI FORTH.
Firmware for IceTea is written in Verilog and swapFORTH, with communication through memory-mapped I/O.
So that TI FORTH (or any language, even TI BASIC) can poke values into registers and invoke interrupts in swapFORTH. For instance my FAT32 SD driver in swapFORTH could be invoked from TI FORTH or from a device service routine written in TMS9900 assembly.
Here's some detail:
My pin use
I used 24 pins to interface the BlackIce to a TI-99/4A with TMS9900 microprocessor.
My schematic (this PDF lacks the connector library symbols)
IceTea schematic
The left side 44-pin connector is the TI-99/4A I/O port. The right side is 3 double PMODs to BlackIce. IceTea translates 5V NMOS and TTL to 3.3V at the BlackIce pin.
My board reduces 34 essential pins to 24. It gets there by putting 15 address pins onto 2 serial shifters (ADRIN1, ADRIN2, SRCLK, SHLD). The goal is to free more pins for PMOD peripherals (and make the connector practical.)
8 bidirectional data bus: DB0 - DB7
4 address bus: ADRIN1, ADRIN2, SRCLK, SHLD
2 clock and reset: PHI3, RESET
7 control lines: MEMEN, DBIN, WE, IAQ, RDBENA, DBDIR, A15/CRUOUT
3 cru serial bus: EN_CRUIN, CRUIN, CRUCLK
24 total, on PMOD7-12.
Most of the complexity and debug hours came from the address pin serialization. I save 11 pins (A0 to A14). (Yes I can hear you Knuth.)
First peripheral: PMOD 14 is a 4 pin I2S, jumpered to AUDIOIN at the 44-pin I/O port.
A prefix of B indicates the BlackIce side of a signal name from the 44-pin I/O port.
I don't see a way to reduce the pin count much further (certainly not 16 pins). I actually want to drive two more pins to the 44-pin connector: LOAD and READY. I considered using a '595 to serialize the data bus. This might save 4 pins but makes meeting timing impossible on read cycles. Maybe save 1 pin if output BCRUIN could double with BDB0.
Some timing constraints
The 44-pin I/O port memory cycle expects slow memories with 2 wait states, for 1 us total per byte (always in 2 byte transactions). This is generous enough to live with address bus serialization.
With the '165s shifting 1 bit per 40 ns, the whole address decode takes 360 ns. I tried to cut this in half to 180 ns for address decode, but one of my '165s stops working when pushed. A 10ns setup time between edges seems to fail (spec is at 9ns).
CRU (a separate i/o memory space) is broken until I achieve 180 ns. CRU read and write single bit cycles are just 333 ns. I must decode the address and set up CRUIN (or read CRUOUT) in this time.
The 44-pin memory bus gives 2 wait states for an overall 1 us per byte transferred. A future goal is to disable the wait states, for a memory cycle of 333 ns, and use a 16-bit data bus. So the address decode must get to 180 ns for that too.
Some wishes
Ideally I could have multiplexed the pins to the SRAM. Having 15 bits of address and 16 bits of data bus without using up all the PMODs would be ideal. My serialization would go away. Most of the time, my code leaves the SRAM pins completely idle except for a few clocks inside the slow 2 us memory cycle. With a multiplexed bus, BlackIce would act as a DMA controller to the TMS9900, asserting READY and sampling HOLDA (hold acknowledge) to reserve the bus for its SRAM access. A board with no built-in SRAM would also free up pins for this.
What works now
Memory cycles from TI-99/4A to pages of the 512k sram.
The sound generator (with waveforms preloaded in BRAM) emulating multiple TMS9919/SN76489.
The FAT32 SD driver in swapFORTH reads directories and files.
What isn't written yet
multiport access to SRAM from swapFORTH and IceTea
moving waveforms from SRAM to BRAM
serial port loopback from swapFORTH to TI FORTH
It seems like a meager progress but all of it has been learned the hard way.
The utterly ridiculous goal to reach is using a TiPi board running the IceStorm tool chain. At that point you'll be able to edit your Verilog on the TI-99/4A in say TI Writer, hit "Print" and have it replace the BlackIce bitstream. Why not? I made sure TiPi can plug into IceTea.
Spare monikers
My board is labeled "SweetTea" while the overall project and firmware is called IceTea. It's a Texas thing.
