It is a two-part process, first you must ensure that APIO recognizes the board and then you must modify several json files in IceStudio, to ensure correct synthesizing. There is a json file where the pins are defined (for some reason the IceStudio team prefers to use a second file and not directly read the PCF). The detection of the board is done through the idVendor and idProduct values of the USB port, seeking not to have to select a communications port. In principle it is interesting, but you can only connect one board at a time.
For IceStudio and APIO (a tool that connects Yosys + Arachne + Icepack) and allows the bitstream to be uploaded to the board, it is transparent if core + carrier or carrier PCF is used, although I understand that if the carrier is modified, at least the names of the pins can change.
What I should highlight is the support and proactivity of the FPGAwars team, they answer almost in real time and are very interested in looking for collaborators to continue growing the project. The main language for interaction is Spanish, although I think almost everyone speaks and writes English.
I think IceStudio version 0.5.1 will contain support for BlackIce MX and will be ready as Nightly version in less than a week