I decided to learn SpinalHDL so I am afraid it is in that rather than Verilog: https://github.com/AndrewCapon/IceCore/tree/USB-CDC-issue-3/TestQSPI
Do you actually need anything on the slave end though?
Also my logic analyser is pretty slow so I am using: hqspi.Init.ClockPrescaler = 200; and a 6.2Mhz clock on the logic.
If you want to just use the Verilog chip.v, pll.v and chip.pcf are here: https://github.com/AndrewCapon/IceCore/tree/USB-CDC-issue-3/TestQSPI/hdl
And here is the generated verilog:
// Generator : SpinalHDL v1.3.5 git head : f0505d24810c8661a24530409359554b7cfa271a
// Date : 12/08/2019, 07:14:58
// Component : MyTopLevel
`define fsm_enumDefinition_binary_sequential_type [2:0]
`define fsm_enumDefinition_binary_sequential_boot 3'b000
`define fsm_enumDefinition_binary_sequential_fsm_stateWaitSS 3'b001
`define fsm_enumDefinition_binary_sequential_fsm_stateDecode 3'b010
`define fsm_enumDefinition_binary_sequential_fsm_stateReceive 3'b011
`define fsm_enumDefinition_binary_sequential_fsm_stateSend 3'b100
module BufferCC (
input io_dataIn,
output io_dataOut,
input clk,
input reset);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @ (posedge clk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
//BufferCC_1_ remplaced by BufferCC
//BufferCC_2_ remplaced by BufferCC
module LedGlow (
output io_led,
input clk,
input reset);
wire [3:0] _zz_1_;
wire [4:0] _zz_2_;
wire [4:0] _zz_3_;
reg [23:0] cnt;
reg [4:0] pwm;
reg [3:0] pwmInput;
assign _zz_1_ = pwm[3 : 0];
assign _zz_2_ = {1'd0, _zz_1_};
assign _zz_3_ = {1'd0, pwmInput};
always @ (*) begin
if(cnt[23])begin
pwmInput = cnt[22 : 19];
end else begin
pwmInput = (~ cnt[22 : 19]);
end
end
assign io_led = pwm[4];
always @ (posedge clk) begin
cnt <= (cnt + (24'b000000000000000000000001));
pwm <= (_zz_2_ + _zz_3_);
end
endmodule
module QspiSlaveCtrl (
input io_kind_cpol,
input io_kind_cpha,
output io_rx_valid,
output [7:0] io_rx_payload,
input io_tx_valid,
output io_tx_ready,
input [7:0] io_tx_payload,
output io_txError,
output io_ssFilted,
input io_spi_sclk,
input io_spi_io0,
output io_spi_io1_write,
output io_spi_io1_writeEnable,
input io_spi_ss,
output io_dbg1,
output io_dbg2,
output io_dbg3,
output io_dbg4,
input clk,
input reset);
wire bufferCC_3__io_dataOut;
wire bufferCC_4__io_dataOut;
wire bufferCC_5__io_dataOut;
wire [0:0] _zz_2_;
wire [3:0] _zz_3_;
wire [8:0] _zz_4_;
wire [2:0] _zz_5_;
wire [2:0] _zz_6_;
wire spi_sclk;
wire spi_io0;
wire spi_io1_write;
wire spi_io1_writeEnable;
wire spi_ss;
wire _zz_1_;
wire normalizedSclkEdges_rise;
wire normalizedSclkEdges_fall;
wire normalizedSclkEdges_toggle;
reg _zz_1__regNext;
wire shit;
reg counter_willIncrement;
reg counter_willClear;
reg [3:0] counter_valueNext;
reg [3:0] counter_value;
wire counter_willOverflowIfInc;
wire counter_willOverflow;
reg [7:0] buffer_1_;
reg counter_willOverflow_regNext;
wire rspBit;
reg rspBitSampled;
assign _zz_2_ = counter_willIncrement;
assign _zz_3_ = {3'd0, _zz_2_};
assign _zz_4_ = {buffer_1_,spi_io0};
assign _zz_5_ = ((3'b111) - _zz_6_);
assign _zz_6_ = (counter_value >>> 1);
BufferCC bufferCC_3_ (
.io_dataIn(io_spi_sclk),
.io_dataOut(bufferCC_3__io_dataOut),
.clk(clk),
.reset(reset)
);
BufferCC bufferCC_4_ (
.io_dataIn(io_spi_ss),
.io_dataOut(bufferCC_4__io_dataOut),
.clk(clk),
.reset(reset)
);
BufferCC bufferCC_5_ (
.io_dataIn(io_spi_io0),
.io_dataOut(bufferCC_5__io_dataOut),
.clk(clk),
.reset(reset)
);
assign spi_sclk = bufferCC_3__io_dataOut;
assign spi_ss = bufferCC_4__io_dataOut;
assign spi_io0 = bufferCC_5__io_dataOut;
assign io_spi_io1_write = spi_io1_write;
assign io_spi_io1_writeEnable = spi_io1_writeEnable;
assign _zz_1_ = ((spi_sclk ^ io_kind_cpol) ^ io_kind_cpha);
assign normalizedSclkEdges_rise = ((! _zz_1__regNext) && _zz_1_);
assign normalizedSclkEdges_fall = (_zz_1__regNext && (! _zz_1_));
assign normalizedSclkEdges_toggle = (_zz_1__regNext != _zz_1_);
assign shit = ((spi_sclk ^ io_kind_cpol) ^ io_kind_cpha);
always @ (*) begin
counter_willIncrement = 1'b0;
if(! spi_ss) begin
if(normalizedSclkEdges_toggle)begin
counter_willIncrement = 1'b1;
end
end
end
always @ (*) begin
counter_willClear = 1'b0;
if(spi_ss)begin
counter_willClear = 1'b1;
end
end
assign counter_willOverflowIfInc = (counter_value == (4'b1111));
assign counter_willOverflow = (counter_willOverflowIfInc && counter_willIncrement);
always @ (*) begin
counter_valueNext = (counter_value + _zz_3_);
if(counter_willClear)begin
counter_valueNext = (4'b0000);
end
end
assign io_ssFilted = spi_ss;
assign io_rx_valid = counter_willOverflow_regNext;
assign io_rx_payload = buffer_1_;
assign io_tx_ready = (counter_willOverflow || spi_ss);
assign io_txError = (io_tx_ready && (! io_tx_valid));
assign rspBit = io_tx_payload[_zz_5_];
assign spi_io1_writeEnable = (! spi_ss);
assign spi_io1_write = (io_kind_cpha ? rspBitSampled : rspBit);
assign io_dbg1 = io_rx_valid;
assign io_dbg2 = io_tx_ready;
assign io_dbg3 = io_txError;
assign io_dbg4 = rspBit;
always @ (posedge clk) begin
_zz_1__regNext <= _zz_1_;
if(! spi_ss) begin
if(normalizedSclkEdges_rise)begin
buffer_1_ <= _zz_4_[7:0];
end
end
counter_willOverflow_regNext <= counter_willOverflow;
if(normalizedSclkEdges_fall)begin
rspBitSampled <= rspBit;
end
end
always @ (posedge clk) begin
if(reset) begin
counter_value <= (4'b0000);
end else begin
counter_value <= counter_valueNext;
end
end
endmodule
module MyTopLevel (
output reg [3:0] io_leds,
input io_io0,
output io_io1,
input io_ss,
input io_sclk,
output io_dbg_io0,
output io_dbg_io1,
output io_dbg_ss,
output io_dbg_sclk,
output io_dbg_1,
output io_dbg_2,
output reg io_dbg_3,
output reg io_dbg_4,
input clk,
input reset);
wire _zz_2_;
wire _zz_3_;
wire _zz_4_;
wire [7:0] _zz_5_;
wire ledGlow_1__io_led;
wire qspiSlaveCtrl_1__io_rx_valid;
wire [7:0] qspiSlaveCtrl_1__io_rx_payload;
wire qspiSlaveCtrl_1__io_tx_ready;
wire qspiSlaveCtrl_1__io_txError;
wire qspiSlaveCtrl_1__io_ssFilted;
wire qspiSlaveCtrl_1__io_spi_io1_write;
wire qspiSlaveCtrl_1__io_spi_io1_writeEnable;
wire qspiSlaveCtrl_1__io_dbg1;
wire qspiSlaveCtrl_1__io_dbg2;
wire qspiSlaveCtrl_1__io_dbg3;
wire qspiSlaveCtrl_1__io_dbg4;
wire _zz_6_;
wire _zz_7_;
wire [0:0] _zz_8_;
wire [7:0] _zz_9_;
reg _zz_1_;
wire rxValidEdges_rise;
wire rxValidEdges_fall;
wire rxValidEdges_toggle;
reg qspiSlaveCtrl_1__io_rx_valid_regNext;
wire txReadyEdges_rise;
wire txReadyEdges_fall;
wire txReadyEdges_toggle;
reg qspiSlaveCtrl_1__io_tx_ready_regNext;
reg [7:0] sendByte;
wire fsm_wantExit;
reg fsm_counter_willIncrement;
wire fsm_counter_willClear;
reg [7:0] fsm_counter_valueNext;
reg [7:0] fsm_counter_value;
wire fsm_counter_willOverflowIfInc;
wire fsm_counter_willOverflow;
reg `fsm_enumDefinition_binary_sequential_type fsm_stateReg;
reg `fsm_enumDefinition_binary_sequential_type fsm_stateNext;
`ifndef SYNTHESIS
reg [127:0] fsm_stateReg_string;
reg [127:0] fsm_stateNext_string;
`endif
reg [7:0] mem [0:255];
assign _zz_6_ = (txReadyEdges_rise || (fsm_counter_value == (8'b00000000)));
assign _zz_7_ = (io_ss == 1'b0);
assign _zz_8_ = fsm_counter_willIncrement;
assign _zz_9_ = {7'd0, _zz_8_};
always @ (posedge clk) begin
if(_zz_1_) begin
mem[fsm_counter_value] <= qspiSlaveCtrl_1__io_rx_payload;
end
end
assign _zz_5_ = mem[fsm_counter_value];
LedGlow ledGlow_1_ (
.io_led(ledGlow_1__io_led),
.clk(clk),
.reset(reset)
);
QspiSlaveCtrl qspiSlaveCtrl_1_ (
.io_kind_cpol(_zz_2_),
.io_kind_cpha(_zz_3_),
.io_rx_valid(qspiSlaveCtrl_1__io_rx_valid),
.io_rx_payload(qspiSlaveCtrl_1__io_rx_payload),
.io_tx_valid(_zz_4_),
.io_tx_ready(qspiSlaveCtrl_1__io_tx_ready),
.io_tx_payload(sendByte),
.io_txError(qspiSlaveCtrl_1__io_txError),
.io_ssFilted(qspiSlaveCtrl_1__io_ssFilted),
.io_spi_sclk(io_sclk),
.io_spi_io0(io_io0),
.io_spi_io1_write(qspiSlaveCtrl_1__io_spi_io1_write),
.io_spi_io1_writeEnable(qspiSlaveCtrl_1__io_spi_io1_writeEnable),
.io_spi_ss(io_ss),
.io_dbg1(qspiSlaveCtrl_1__io_dbg1),
.io_dbg2(qspiSlaveCtrl_1__io_dbg2),
.io_dbg3(qspiSlaveCtrl_1__io_dbg3),
.io_dbg4(qspiSlaveCtrl_1__io_dbg4),
.clk(clk),
.reset(reset)
);
`ifndef SYNTHESIS
always @(*) begin
case(fsm_stateReg)
`fsm_enumDefinition_binary_sequential_boot : fsm_stateReg_string = "boot ";
`fsm_enumDefinition_binary_sequential_fsm_stateWaitSS : fsm_stateReg_string = "fsm_stateWaitSS ";
`fsm_enumDefinition_binary_sequential_fsm_stateDecode : fsm_stateReg_string = "fsm_stateDecode ";
`fsm_enumDefinition_binary_sequential_fsm_stateReceive : fsm_stateReg_string = "fsm_stateReceive";
`fsm_enumDefinition_binary_sequential_fsm_stateSend : fsm_stateReg_string = "fsm_stateSend ";
default : fsm_stateReg_string = "????????????????";
endcase
end
always @(*) begin
case(fsm_stateNext)
`fsm_enumDefinition_binary_sequential_boot : fsm_stateNext_string = "boot ";
`fsm_enumDefinition_binary_sequential_fsm_stateWaitSS : fsm_stateNext_string = "fsm_stateWaitSS ";
`fsm_enumDefinition_binary_sequential_fsm_stateDecode : fsm_stateNext_string = "fsm_stateDecode ";
`fsm_enumDefinition_binary_sequential_fsm_stateReceive : fsm_stateNext_string = "fsm_stateReceive";
`fsm_enumDefinition_binary_sequential_fsm_stateSend : fsm_stateNext_string = "fsm_stateSend ";
default : fsm_stateNext_string = "????????????????";
endcase
end
`endif
always @ (*) begin
_zz_1_ = 1'b0;
case(fsm_stateReg)
`fsm_enumDefinition_binary_sequential_fsm_stateWaitSS : begin
end
`fsm_enumDefinition_binary_sequential_fsm_stateDecode : begin
end
`fsm_enumDefinition_binary_sequential_fsm_stateReceive : begin
if(rxValidEdges_rise)begin
_zz_1_ = 1'b1;
end
end
`fsm_enumDefinition_binary_sequential_fsm_stateSend : begin
end
default : begin
end
endcase
end
assign _zz_3_ = 1'b0;
assign _zz_2_ = 1'b0;
assign _zz_4_ = 1'b1;
assign io_io1 = qspiSlaveCtrl_1__io_spi_io1_write;
always @ (*) begin
io_leds[0] = (! io_io0);
io_leds[1] = (! io_io1);
io_leds[2] = (! io_ss);
io_leds[3] = (! io_sclk);
end
assign io_dbg_io0 = io_io0;
assign io_dbg_io1 = io_io1;
assign io_dbg_ss = io_ss;
assign io_dbg_sclk = io_sclk;
always @ (*) begin
io_dbg_3 = 1'b0;
case(fsm_stateReg)
`fsm_enumDefinition_binary_sequential_fsm_stateWaitSS : begin
end
`fsm_enumDefinition_binary_sequential_fsm_stateDecode : begin
end
`fsm_enumDefinition_binary_sequential_fsm_stateReceive : begin
end
`fsm_enumDefinition_binary_sequential_fsm_stateSend : begin
io_dbg_3 = 1'b1;
end
default : begin
end
endcase
end
always @ (*) begin
io_dbg_4 = 1'b0;
case(fsm_stateReg)
`fsm_enumDefinition_binary_sequential_fsm_stateWaitSS : begin
end
`fsm_enumDefinition_binary_sequential_fsm_stateDecode : begin
end
`fsm_enumDefinition_binary_sequential_fsm_stateReceive : begin
end
`fsm_enumDefinition_binary_sequential_fsm_stateSend : begin
if(_zz_6_)begin
io_dbg_4 = 1'b1;
end
end
default : begin
end
endcase
end
assign rxValidEdges_rise = ((! qspiSlaveCtrl_1__io_rx_valid_regNext) && qspiSlaveCtrl_1__io_rx_valid);
assign rxValidEdges_fall = (qspiSlaveCtrl_1__io_rx_valid_regNext && (! qspiSlaveCtrl_1__io_rx_valid));
assign rxValidEdges_toggle = (qspiSlaveCtrl_1__io_rx_valid_regNext != qspiSlaveCtrl_1__io_rx_valid);
assign txReadyEdges_rise = ((! qspiSlaveCtrl_1__io_tx_ready_regNext) && qspiSlaveCtrl_1__io_tx_ready);
assign txReadyEdges_fall = (qspiSlaveCtrl_1__io_tx_ready_regNext && (! qspiSlaveCtrl_1__io_tx_ready));
assign txReadyEdges_toggle = (qspiSlaveCtrl_1__io_tx_ready_regNext != qspiSlaveCtrl_1__io_tx_ready);
assign io_dbg_1 = qspiSlaveCtrl_1__io_tx_ready;
assign io_dbg_2 = txReadyEdges_rise;
assign fsm_wantExit = 1'b0;
always @ (*) begin
fsm_counter_willIncrement = 1'b0;
case(fsm_stateReg)
`fsm_enumDefinition_binary_sequential_fsm_stateWaitSS : begin
end
`fsm_enumDefinition_binary_sequential_fsm_stateDecode : begin
end
`fsm_enumDefinition_binary_sequential_fsm_stateReceive : begin
if(rxValidEdges_rise)begin
fsm_counter_willIncrement = 1'b1;
end
end
`fsm_enumDefinition_binary_sequential_fsm_stateSend : begin
if(_zz_6_)begin
fsm_counter_willIncrement = 1'b1;
end
end
default : begin
end
endcase
end
assign fsm_counter_willClear = 1'b0;
assign fsm_counter_willOverflowIfInc = (fsm_counter_value == (8'b11111111));
assign fsm_counter_willOverflow = (fsm_counter_willOverflowIfInc && fsm_counter_willIncrement);
always @ (*) begin
fsm_counter_valueNext = (fsm_counter_value + _zz_9_);
if(fsm_counter_willClear)begin
fsm_counter_valueNext = (8'b00000000);
end
end
always @ (*) begin
fsm_stateNext = fsm_stateReg;
case(fsm_stateReg)
`fsm_enumDefinition_binary_sequential_fsm_stateWaitSS : begin
if(_zz_7_)begin
fsm_stateNext = `fsm_enumDefinition_binary_sequential_fsm_stateDecode;
end
end
`fsm_enumDefinition_binary_sequential_fsm_stateDecode : begin
if(rxValidEdges_rise)begin
if((qspiSlaveCtrl_1__io_rx_payload == (8'b00000001)))begin
fsm_stateNext = `fsm_enumDefinition_binary_sequential_fsm_stateReceive;
end else begin
if((qspiSlaveCtrl_1__io_rx_payload == (8'b00000010)))begin
fsm_stateNext = `fsm_enumDefinition_binary_sequential_fsm_stateSend;
end
end
end
if(io_ss)begin
fsm_stateNext = `fsm_enumDefinition_binary_sequential_fsm_stateWaitSS;
end
end
`fsm_enumDefinition_binary_sequential_fsm_stateReceive : begin
if(io_ss)begin
fsm_stateNext = `fsm_enumDefinition_binary_sequential_fsm_stateWaitSS;
end
end
`fsm_enumDefinition_binary_sequential_fsm_stateSend : begin
if(io_ss)begin
fsm_stateNext = `fsm_enumDefinition_binary_sequential_fsm_stateWaitSS;
end
end
default : begin
fsm_stateNext = `fsm_enumDefinition_binary_sequential_fsm_stateWaitSS;
end
endcase
end
always @ (posedge clk) begin
qspiSlaveCtrl_1__io_rx_valid_regNext <= qspiSlaveCtrl_1__io_rx_valid;
qspiSlaveCtrl_1__io_tx_ready_regNext <= qspiSlaveCtrl_1__io_tx_ready;
case(fsm_stateReg)
`fsm_enumDefinition_binary_sequential_fsm_stateWaitSS : begin
if(_zz_7_)begin
sendByte <= (8'b00000000);
end
end
`fsm_enumDefinition_binary_sequential_fsm_stateDecode : begin
end
`fsm_enumDefinition_binary_sequential_fsm_stateReceive : begin
end
`fsm_enumDefinition_binary_sequential_fsm_stateSend : begin
if(_zz_6_)begin
sendByte <= _zz_5_;
end
end
default : begin
end
endcase
end
always @ (posedge clk) begin
if(reset) begin
fsm_counter_value <= (8'b00000000);
fsm_stateReg <= `fsm_enumDefinition_binary_sequential_boot;
end else begin
fsm_counter_value <= fsm_counter_valueNext;
fsm_stateReg <= fsm_stateNext;
if(((! (fsm_stateReg == `fsm_enumDefinition_binary_sequential_fsm_stateReceive)) && (fsm_stateNext == `fsm_enumDefinition_binary_sequential_fsm_stateReceive)))begin
fsm_counter_value <= (8'b00000000);
end
if(((! (fsm_stateReg == `fsm_enumDefinition_binary_sequential_fsm_stateSend)) && (fsm_stateNext == `fsm_enumDefinition_binary_sequential_fsm_stateSend)))begin
fsm_counter_value <= (8'b00000000);
end
end
end
endmodule
