I have been working with the CS4344 on the Digilent I2S PMOD with no success at getting audio out. Can anyone help me with some ideas what to try next? [EDIT: ARG! I had the SDIN and SCLK pins switched in my chip.v and it works now.]
I2S is connected to PMOD 6 (I'm using PMOD 5 for some extra bits as well.) There is a Digilent TPH2 which I suspect introduces a lot of noise, for my logic analyzer. I tested with and without the TPH2 in between.
I suspect my MCLK is not that great. I configured (using ICEPLL) a 32.768 MHz clock, which I divide by counting pulses to 8.192 MHz (after trying several higher clocks I settled on the lowest one in the datasheet.) Here is a capture of my clock (in full bandwidth mode.) MCLK is in red, LRCLK is in yellow. I don't know if the ringing (-500mV below 0, +500 mV above VCC) is real, just on my probe, or damaging to the device. The MCLK is just an ordinary output pin.
There are a lot of glitches seen at my logic analyzer (with high level configured at 2.0V) that I don't see when I use the scope. I don't think those are affecting the I2S. I get more glitches when I add high frequency signals on bits0-3 pins, and more glitches using the TPH2 vs just probing directly off the BlackIce board.
Here are some samples decoded from the SDIN/SCLK channel. I'm sending a simple 256Hz square wave as 1F and E1, but the decoder sees a leading 0 (CS4344 requires a 1 cycle lag) so they show up as 0F 80 or 03 C0.
And here is my i2s.v module code:
module i2s(i_sample, clk, reset, o_mclk, o_lrclk, o_sdin, o_sclk);
// clk and reset are the i2s clk 28.646 MHz and global reset (not synchronous)
// I will take clk at 8.192 MHz
// divide it by 256 to get o_lrclk at 32 kHz,
// with o_sclk at 7.1615 MHz, or 64 clocks, or 32 bits per sample channel.
// Recommendations for powerup:
// o_mclk be applied for 250 ms before o_lrclk to charge internal caps.
// no action required: device outputs 0 for first 2000 samples.
// Feed 0 data for 10 samples while changing o_lrclk ratio.
parameter WIDTH = 8;
input [WIDTH-1 : 0] i_sample;
input wire clk, reset;
output wire o_mclk;
output wire o_lrclk, o_sdin, o_sclk;
reg [23 : 0 ] i; // 8 bits for stereo cycle, but 24 bits to count until startup charging delay
reg [WIDTH-1 : 0] shifter; // only 24 bits are significant to CS4344; only WIDTH bits are loaded.
reg resetn = 0;
assign o_mclk = clk; // 8.192 MHz
assign o_sclk = resetn & i; // 2.048 MHz
assign o_lrclk = resetn & i; // 32 kHz
assign o_sdin = resetn & shifter[WIDTH-1];
// ratio of o_lrclk/o_mclk is 256
// ratio of o_sclk/o_mclk is 64
// o_sdin must be stable on posedge o_sclk.
// o_lrclk changes on posedge o_mclk
always @(posedge reset or posedge clk)
i <= 24'h000;
shifter <= 0;
resetn <= 0;
i = i + 1;
if (i[6:0] == 8'h04)
// load shift register after 1 idle sclk (mclk/4) cycle
shifter = i_sample;
else if (i[1:0] == 2'b00)
// Shift on every 1 sclk falling edge thereafter
shifter <= shifter << 1;
if (i) // delay at least 250 ms
resetn <= 1;
endmodule // i2s
Thank you in advance for any suggestions.
[EDIT: It is now outputting a clear square wave. It sounds sweet, like 12 hours of effort.]