There are lots of things that take some getting used to. The python style lists and slices are LSB-first and the end point of the range is non-inclusive so that foo[7:0]
in Verilog becomes foo[0:8]
in nmigen.
Then Cat(...)
is LSB-first as opposed to Verilog's { .... }
.
A common source of bugs for me is to forget the m.d.sync +=
particularly after ifs (with m.If(...):
) with a single statement.