Getting started with nMigen

[BigEd]

Can anyone provide some links to tried and tested briefings, or tutorials, or demonstrations, of nMigen in action?

[lawrie]

This is probably the best nmigen tutorial - https://github.com/RobertBaruch/nmigen-tutorial

And there is this - http://blog.lambdaconcept.com/doku.php?id=nmigen:tutorial

And this - https://vivonomicon.com/2020/04/14/learning-fpga-design-with-nmigen/

And there is this video - https://www.youtube.com/watch?v=yDJNwxY05-s&list=UUf2O7PWyhBZYOAn2LJo6xMg

[lawrie]

For examples there is my repository - https://github.com/lawrie/ulx3s-nmigen-examples

And esden's - https://github.com/icebreaker-fpga/icebreaker-nmigen-examples

And kbob's - https://github.com/kbob/nmigen-examples

[lawrie]

There is this language guide, but it is not complete - https://nmigen.info/nmigen/latest/lang.html

[lawrie]

For interesting nmigen projects, there is:

minerva (risc-v) - https://github.com/lambdaconcept/minerva

lambda-soc (which uses minerva) - https://github.com/lambdaconcept/lambdasoc

luna (usb devices and sniffers) - https://github.com/greatscottgadgets/luna

6800 CPU - https://github.com/RobertBaruch/n6800

And a series of videos by Robert Baruch on building the 6800 CPU - https://www.youtube.com/watch?v=85ZCTuekjGA&list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw

Also the Boneless CPU by the author of nmigen - https://github.com/whitequark/Boneless-CPU

(That should all keep you occupied for a while).

[BigEd]

Many thanks! I read a little of the tutorial and was taken aback by bit vectors being LSB-first. I hope that's not insurmountable - feels like a likely cause of bugs and brain-strain.

[lawrie]

There are lots of things that take some getting used to. The python style lists and slices are LSB-first and the end point of the range is non-inclusive so that foo[7:0] in Verilog becomes foo[0:8] in nmigen.

Then Cat(...) is LSB-first as opposed to Verilog's { .... }.

A common source of bugs for me is to forget the m.d.sync += particularly after ifs (with m.If(...):) with a single statement.

[lawrie]

I see that Robert Baruch has rebooted his Risc-V project and this time he is using nmigen with formal verification to help him design a Risc-V implementation that will use a multitude of real physical chips (not an FPGA) - https://www.youtube.com/watch?v=YgXJf8c5PLo