Flash programming on Blackice Mx

[lawrie]

After a bit of difficulty, I now have SB_WARMBOOT working.

So on power-on, my writeflash SoC runs. I can then send it a bistream to write to slot 1 (0x28000) and warm boot to it.

I don't need that STM32 processor and usb programming port any more

The latest version of the SoC is in the repository.

[lawrie]

And I now have a SoC that support execute-in-place (XIP), i.e it executes Risc-V code directly from the flash memory, I am using address 0x50000 for this, and using my writeflash SoC to write the XIP SoC image to address 0x28000, as XIP only works if the image is booted from flash memory (as the SaxonSoc XIP code does not wake up flash memory).

[almejia]

Hi Lawrie, looking for a hardware test platform for my students of Computer Architecture, we would like to use BlackIce MX for testing software developed for RiscV processor. I already uploaded this soc to BlackIce MX but I'm not able to load a compiled binary and run it from flash

I can not see messages on second serial (tyyUSB0), therefore I did not know if it is saving data in flash or not

Could you explain me a little more , how to test it?

[Folknology]

For BlackIce Mx we do not use the 2nd USB, the serial (and loading) uses the 1st usb (nearest the corner) and normally appears as ttyAcm0 on linux:

to setup the serial issue
stty -F /dev/ttyACM0 raw

The load the binary
cat chip.bin >/dev/ttyACM0

Afterwards to see output use
cat /dev/ttyACM0

Hope this helps

[lawrie]

Hi Lawrie, looking for a hardware test platform for my students of Computer Architecture, we would like to use BlackIce MX for testing software developed for RiscV processor. I already uploaded this soc to BlackIce MX but I'm not able to load a compiled binary and run it from flash

Hi @almejia, It is a while since I worked on Risc-V SoCs on the Blackice Mx., and I believe I had multiple Risc-V SoCs working.

Can you tell me which SoC you are using from which repository?

[almejia]

I'm using the one in blackicemx_examples repo
By the way I understand it is defined in SpinalHDL, where I can define the pinout for different periferals?

In fact if you have a better SoC for RISCV with the capability of upload hex files (RiscV compiled programs) will be better

Thanks

[lawrie]

Hi @almejia,

I am just having a look at this.

This thread is very old and I was using an external usb to serial device at the time as the Icecore firmware did not support a uart at the time I was doing this. It was added later and used /dev/ttyACM0. The external usb to serial device used /dev/ttyUSB0.

The icecore firmware still does not support writing an image to the flash apart from a bitstream at address 0, so my writeflash utility is still useful, but the instructions for using it are a bit different to the ones in this thread.

The writeflash utility is written using the risc-v saxonsoc, but its only purpose is to write an image to the flash memory. It does not run a risc-v program. But you can use a different saxonsoc bitstream to run a risc-v program from flash.

I had a variety of risc-v systems running on the Blackice Mx board. Some ran the risc-v program from flash memory, some ran it from BRAM and some loaded it into SDRAM and ran it from there. None of them had much testing and there were some issues with them that I never properly diagnosed.

I either used SaxonSoc with the VexRiscv cpu, or I used variants of picosoc or icosoc with the picorv32 cpu.

I am not sure which is easiest for your students to use.

For using SaxonSoc, this thread is a bit more up to date - https://forum.mystorm.uk/t/running-saxonsoc-on-blackice-mx

However, SaxonSoc has moved on a lot since then, and has had some incompatible changes, so I don't know if all that still works.

The instructions for using writeflash in that thread are more accurate than the ones in this thread.

An alternative to SaxonSoc is BlackSoc, which uses picorv32. With that the risc-v program is loaded over the uart link (/dev/ttyACM0) and runs from SDRAM.

Another alternative is pico_xip_soc which is described in this thread - https://forum.mystorm.uk/t/pacman-game-using-pico-xip-soc/733

That again uses picorv32, but runs the program from flash memory using execute-in place, so needs writeflash to write the image to the flash memory.

The very simpest of the risc-v Socs that I produced is described in this thread - https://forum.mystorm.uk/t/pico-ram-soc-on-blackice-mx

Again it uses picorv32, but just runs very small risc-v programs from BRAM.

As I say, I am not sure which of these (if any) suit your requirement.

[lawrie]

To see a risc-v program running from flash memory, you can use the pacman.bin file in the writeflash directory in blackicemx_examples. That file has the prefix prepended to it, so if you run the writeflash bitstream, do stty -F /dev/ttyACM0 -echo raw 115200; cat /dev/ttyACM0 and then cat pacman.bin >/dev./ttyACM0 in another terminal, you should see the output showing pacman.bin being written to address 0x50000 in flash memory.

You should see a lot of output, starting:

Program Flash memory

Address: 00050000
Length:0000F85C

Data:

000000 0600600B 15C0006F 00000013 00000013 0200A10B 0201218B

If you then go to pico_xip_soc/games/pacman and do 'make` it should upload the pico_xip_soc bitstream and start running the pacman game. You might meed to edit the make files if your riscv compiler is in a different place. It should work with most risc-v compilers.

To see that the Pacman game is running, you will need a Digilent VGA Pmod plugged into the slot opposite the usb connectors. It is currently working for me. To play the game, you need a Wii controller and an adapter. If you connect a speaker to the relevant pins, you should be able to hear audio also.

[almejia]

Thank you Lawrie!!! A lot of very good information I will check today
Sorry to not answer during weekend, but I have 2 little girls that claim attention!!

Have a nice week

[almejia]

I will test it today! Thank you

[almejia]

Hi Lawrie,
I make a python script to make writeflash even more simple, I tested it and works fine,

syntax
python prog.py --address 0x50000 --port /dev/cu.usbmodem00000000001A1 simple.bin

prog.py:

import struct
import sys
import os
import platform
import argparse

# Configure parse parameters
parser = argparse.ArgumentParser(description='Process arguments.')
parser.add_argument('--address', nargs='?', default=0x50000,help='Address')
parser.add_argument('--port', nargs='?', default='/dev/ttyACM0',help='Port')
parser.add_argument('filename')

#read parse arguments
args = parser.parse_args()

#extract values
addr = int(args.address,0)
filename = args.filename
length = os.stat(filename).st_size
port = args.port

#print arguments (just for debug)
print('File:', filename)
print('Size:', length)
print('Address:', addr)
print('Port:', port)

# create prefix file
prefix = open("prefix.bin", mode='wb') 
prefix.write(struct.pack('>I', addr))
prefix.write(struct.pack('>I', length))
prefix.close()

# concatenate binary file to prefix
with open("prefix.bin", "ab") as myfile, open(filename, "rb") as file2:
    myfile.write(file2.read())

#detect platform
platform = platform.system()

#print platform for debug
print('Platform:', platform)


if(platform == 'Linux'):
    # send commads if platform == Linux
    cmd = 'stty -F ' + port + ' raw -echo 115200'
    os.system(cmd)
    prog = 'cat prefix.bin > ' + port 
    os.system(prog)
else:
    # send commads if platform == OSX (Darwin)
    cmd = 'stty -f ' + port + ' raw -echo 115200'
    os.system(cmd)
    prog = 'cat prefix.bin > ' + port 
    os.system(prog)

print('Hex file sended to RiscV')

[almejia]

I'm not very familiar with SpinalHDL, but is very interesting project, but I want to make some changes in addressing for input output ports

Main Idea is to use same address that RARS simulator uses for data area, and in/out ports just to test in hardware that students make in simulation... Where I can define those address?

Thank you

[lawrie]

I did briefly look at writing a python wrapper like your one for writeflash, but what I had was sufficient for my need at the time.

I think the diagnostic output from writeflash has some errors in it, probably due to problems with uart overflow, but that does not seem to affect what is written to the flash memory.

SaxonSoc has moved on a lot since I used it on the Blackice boards, and I am not sure if those projects still build. It is currently concentrating on the Linux port to a couple of boards including the Ulx3s board that I use.

For the XIP version, these lines define the addresses used for memory and I/O ports - https://github.com/SpinalHDL/SaxonSoc/blob/Bmb/hardware/scala/saxon/board/blackicemx/BlackiceMxXip.scala#L16-L19

If you change the memory addresses, you would have to change the linker script. I/O addresses should be coped with by the generated bsp header files.

But you might be better off using one of the picorv32 based SoCs as they are more stable than SaxonSoc. SaxonSoc has a lot of experimental stuff in it, which is still changing. There is an older more stable SpinalHDL based SoC called Murax, but I don't think I ever ran that on Blackice Mx (only Blackice II).

There is also the LiteX Soc, which uses the python-based Migen language. That can use VexRiscxv or picorv32, but I have not used that.

Or there is the newer, nmigen based lamba-soc which uses the minerva risc-v cpu. I recently ran that on the Ulx3s board and it should not be hard to get that working on Blackice Mx, but I don't know a lot about it.

I have never looked at RARS.