I have not done anything with ADC devices for a while.
But it may be possible to use one of the SDRAM controllers we now have to do that.
How wide is the ADC data that you want to read (8-bit, 16-bit or 32-bit)? Do you need to read the ADC device continuously? At what speed? How much data at a time?
The SDRAM controller I am using for retro computers does a 16-bit write in 8 cycles with a 64Mhz clock but need some spare groups of 8 cycles to do refreshes. It is probably possible to do writes in fewer cycles.
Using @zipcpu's Wishbone bus SDRAM controller is another possibility. That does 32-bit writes but the number of cycles taken is variable. He says it should be possible to overlap writes and issue them every 2 cycles. You would probably need to do that to keep up with a fast ADC device. I have not tried this.
The other SDRAM controller that I have working is a SpinalHDL SaxonSoc one, but that would probably be difficult to use for this and I don't know how fast it could be made to go. It would probably need a DMA ADC controller.