I got VHDL working with
yosys using the plugin from Clifford's GitHub. I thought I'd document it here in case anyone else is allergic to Verilog like I am
Firstly build yosys et al. in the usual way. If you need help with this, I can do another posting another time.
$ git clone git://github.com/cliffordwolf/yosys-plugins
$ cd yosys-plugins/vhdl
... run your editor on vhdl_frontend.cc ...
In your editor, you need to find the line
log_header("Executing VHDL frontend.\n"); and remove the
_header so that it reads
Now find the call to
AST::process() later in the file, and add
...flag_dump_vlog, flag_nolatches,... so that it reads
...flag_dump_vlog, false, flag_nolatches,...
Now you should:
$ make test
... tests run, ensure they pass...
$ make install
Finally, wherever yosys is invoked in your makefile, add
-m vhdl to its arguments and ensure that VHDL source files end in
.vhd rather than just
.v and things should "just work".
Hope this helps someone,