The CDONE error will be related to the state of the DONE signal which is also effected by the GBIN4 state which is dictated by your Verliog (or last bitfile loaded). If you look at the new PCF file and the tutorials we make DONE and DBG1 inputs to avoid messing with Done state on flashing.:
module chip (
// 100MHz clock input
input clk,
// Global internal reset connected to RTS on ch340 and also PMOD[1]
input greset,
// Input lines from STM32/Done can be used to signal to Ice40 logic
input DONE, // could be used as interupt in post programming
input DBG1, // Could be used to select coms via STM32 or RPi etc..
// SRAM Memory lines
output [18:0] ADR,
output [15:0] DAT,
output RAMOE,
output RAMWE,
output RAMCS,
output RAMLB,
output RAMUB,
// All PMOD outputs
output [55:0] PMOD
);
The 'CDONE not set' error occurs when the state of the DONE signal after programming is not what it is expected to be.
BTW: even if you get the 'CDONE not set' message it still could have succeeded in loading the bitfile into the Ice40, it is just misreading the DONE state signal and jumping to the conclusion that loading failed..
