This is absolutely relevent, @Folknology. Thanks! 26 minutes well spent! Summary, to make this findable in this forum:
Raising the level of abstraction in digital design with Chisel3 and FIRRTL
Jack Koenig, SiFive (https://en.wikipedia.org/wiki/SiFive)
Chisel = Hardware construction language
Chisel Community Conference: https://www.chisel-lang.org
Sponsors: SiFive, Western Digital
To me it looks like and sounds like Chisel is not targeted to push Verilog or VHDL away, but to be a tool to fill out the gaps where these two languages rely on scripts, so that these tools can cooperate. I guess they would mean that Chisel has the potential to take over from Verilog or VHDL, but there are parts that are still not implemented. To me it also looks like and sounds like it's kind of not finished. But from my stupid questions here that's a feeling I surprisingly have about Verilog and VHDL, too. Verry strange, for such old languages and with such an impact in the HW world. This I guess sums up some of it, with more or less meaningful words to me:
Building an ecosystem. Starting with Verilog or Chisel3 which are input to a FIRRTL compiler. The FIRRTL compiler outputs Verilog, C++ or Scala plus it seems to cooperate with BIST/JTAG Stitching, FPGA Snapshotting, FPGA Assertions, FPGA Clock Decoupling - and Early Area Estimation, ASIC SRAMS, Floorplanning Hints and Retiming.