C2 is a simple 5-stage RISC, with a custom ISA designed primarily for experimenting with extended instructions. Explicit delay slots, SRAM only (memory access does not stall the pipeline), no interrupts. There is a not yet published compatible core though with DDR support, caches and interrupts (being used as an interface node in NoC systems).
The only spec in existence is this, along with the Verilog source and the compiler back-end, of course.
As for clike, it's using an LLVM-compatible IR and can target in theory anything that LLVM targets (tested with x86 and ARM only so far). And it's relatively easy to write your own optimising backends too - all of the C2 target-specific stuff is in this file, and most of it can be shared with pretty much any MIPS-ish small RISC target.
Thanks for pointing at OPC7, it's quite interesting, I'll try to implement a backend for it.