I have produced a simplified version of @ZipCPU's wishbone SDRAM implementation that just does a RAM test.
It uses the wbsdram module unchanged and also genuctrl and iceioddr.
There is a much simplified toplevel.v that has a very simple wishbone master to do the memory test. All other peripherals and the cpu have been removed.
I have changed the clock speed to 64Mhz.
The ram test writes to all the ram (setting the data to its 19-bit address) and then reads it back slowly showing it on an led strip. It appears to be working.
Wbsdram does 32-bit reads and writes (with an optional wb_sel mask to only write specific bytes). It use a 19-bit address field which is a 32-bit word address not a byte address.
My tests seem to show that a read of a 32-bit word takes 12 clock cycles, with the occasional longer one, presumably when it is interrupted by a refresh. At 64Mhz these longer ones seem to take 16 cycles. At 50Mhz, the longer one seemed to take 24 cycles. Writes seem to be quicker, taking 8 cycles.
If this is correct, doing a 16-bit read in 8 cycles at 64Mhz for the Gameboy implementation should not be a problem.
The ram test is currently using about 500 LCs (6%).