Assume you want posted here?
the typos all seem fixed.
There are two PLLs and 960 Programmable Logic Blocks (PLLs) which each consist of a 4 input look-up table (4-LUT) and a 1-bit D flip-flop. There are 32 blocks, each of 512 bytes, giving a total of 16kb of BRAM.
- Should that read PLB? for Programmable Logic Blocks?
- I assume that should be 16KB or 16kB as it is bytes and not bits.?
Also, I know you did do the pictures but might be useful to add on either the photo or block diagram, which USB port is which, I know when I started I kept getting them mixed up, and getting a mag glass out to read the writing on the board.
Programming Built in Hardware
Few more in this one (I am being nit-picky but might as well do them, most are just consistent capitalisation of LEDs):
This is because of thec way that the user LEDs are wired on the Blackice Mx iceCore board.
Note that button 1 is wired to the blue user led and button 2 to the green user led, so that thoses LEDs come on when you press the appropriate button.
You don’t need to use Verilog to set an LED when a button is pressed as the buttons are wired to the blue and green LEDS. But if you wanted to set one of the other two LEDs when the button is prsssed, this is how you do it:
Note that -pullup yes is used in the pcf file for the button. Although the Blackice Mx has a pullup resistor on the button, because of the way the buttons are wired to the blue and green user LEDs, that resistore is not sufficient to get reliable signals from a button press, so the internal resistor needs to be enabled.
Note also that the button signal will be high by default and low when the button is prsssed, and that the user leds are set on when their output signal is low, and off when it is high. So no negation is needed when setting the LED signal from the button signal.
Build and upload in the normal way and you should see the led counter increasing by more than one per press.
When you make and run this you should see the led counter increase by 1 for each button press.
The internal memory in the Ice40 FPGA is known as Block RAM or BRAM. There is 16kb of it in 32 banks of 512 bytes.
a Verilog module examines the address and decides whether to map it to SDRAM or BRAM or flash memory, or to interpret it as an a read or write to other hardware.
Not much wrong here that I could see:
There is a professional open source ISA called Risc-V. It is well supported by gnu tool chains and can be considered as an open source alternative to the ARM family of ISAs.
There were just 32 words of 32-but data in the first implementation of the BABy, otherwise known as the Small Scale Experimental Machine.
Nice to have: Would be good to repeat the content/topics section from the first page in the sidebar, and for it to high light which one you are on.
But very good. I still have to read the other pages. If only you had converted it two months ago