A lot of the focus for the BlackEdge project so far has been centred around the introduction of the ECP5, nextpnr and project trellis which is really exciting. However BlackEdge is a bigger idea than the FPGA and tools themselves, it's about how we apply those tools and how we build OpenSource Hardware (OSH) around FPGAs. I have mentioned in the original BlackEdge thread how we are partitioning the hardware to enable 'Cores' & 'Carriers', but I haven't explained any real detail about this, so I want to cover that here.
As a reminder the idea here is that we want to enable the 'Core' modules to be used in both the development boards and kits as well as within an other hardware projects that need OSH FPGA at their heart. That is if I am designing a hardware project for specific applications I would like to use the BlackEdge cores to fulfill the FPGA and High speed roles, whilst the rest of the hardware I can design myself. This avoids having to deal with the really difficult stuff like BGA pinouts, high speed digital video routing and memory interfacing etc.. In other words I can concentrate on the all important application specific hardware and software.
In order to do this I need to consider the connectivity of BlackEdge products, it must be open, standardised (consistent), available and low cost in order to be useful for lots of applications. Here are some considerations for common interconnects:
Headers 0.1 inch, 2.54mm spacing used by many µC dev boards and DIP based modules - great general purpose connectivity, low cost accessible and ubiquitous. This is the kind of solution that is excellent for my* type products and projects. The big disadvantages of these is the low pin density, FPGA have a business model that factors IO pins into their cost. Thus if you are going to shell for the the higher cost FPGAs you want access to as many pins on that package as possible to maximise your value for money..
Many of the current mid to high end FPGA development boards use high density connectors in order to solve the issue above (as well as performance), it sometimes appears to be a vendor competition to use the latest highest performing connectors at premium prices on the dev boards. This has the disadvantage of increasing the dev board cost and more importantly the peripheral or integration costs for anyone wishing to use the hardware inside their own projects.
Clearly something in between is needed, a mid density, easy to add into designs, low cost and hackable connection type. For BlackEdge I plan to use 1.27mm headers, these provide the density that is needed at low cost. They are also available as through hole and surface mount making them more accessible, one can also get hold of these from the common Asian outlets at low cost making them great for hacking etc..
The Physical part of the BlackEdge connectivity is pinout and form factor, so lets tackle that next. The planned form factor of the 'Core' Modules is 50mm x 50mm, this is a convenient size to integrate into a application specific hardware project of development carrier, it fits nicely into the common sizes offered at discounts by many of the Asian PCB suppliers making design and build accessible and low cost for all. The design also houses 4 * 2.5mm holes useful for optionally securing the 'Core' module to the base or carrier board using commonly available low cost standoffs, this adds physical security, important for things like robotics and tougher environments than the desktop..
The planned pinout on the 'Core' modules consist of two dual (25 each) row 50pin female connectors, these mate with similar male connectors on the base or carrier board. This enables the transport of the following signals:
- 4 CNTRL/CONF IO
- 7 Power Supply pins
- 9 JTAG/SWD/PROG
- Up to 16 Mixed signal IO lines
- Up to 64 Digital FPGA IO lines
Looking forward to your thoughts and feedback on the BlackEdge connectivity ideas..