BlackEdge Connectivity

[Folknology]

A lot of the focus for the BlackEdge project so far has been centred around the introduction of the ECP5, nextpnr and project trellis which is really exciting. However BlackEdge is a bigger idea than the FPGA and tools themselves, it's about how we apply those tools and how we build OpenSource Hardware (OSH) around FPGAs. I have mentioned in the original BlackEdge thread how we are partitioning the hardware to enable 'Cores' & 'Carriers', but I haven't explained any real detail about this, so I want to cover that here.

As a reminder the idea here is that we want to enable the 'Core' modules to be used in both the development boards and kits as well as within an other hardware projects that need OSH FPGA at their heart. That is if I am designing a hardware project for specific applications I would like to use the BlackEdge cores to fulfill the FPGA and High speed roles, whilst the rest of the hardware I can design myself. This avoids having to deal with the really difficult stuff like BGA pinouts, high speed digital video routing and memory interfacing etc.. In other words I can concentrate on the all important application specific hardware and software.

In order to do this I need to consider the connectivity of BlackEdge products, it must be open, standardised (consistent), available and low cost in order to be useful for lots of applications. Here are some considerations for common interconnects:

1. Headers 0.1 inch, 2.54mm spacing used by many µC dev boards and DIP based modules - great general purpose connectivity, low cost accessible and ubiquitous. This is the kind of solution that is excellent for my* type products and projects. The big disadvantages of these is the low pin density, FPGA have a business model that factors IO pins into their cost. Thus if you are going to shell for the the higher cost FPGAs you want access to as many pins on that package as possible to maximise your value for money..

2. Many of the current mid to high end FPGA development boards use high density connectors in order to solve the issue above (as well as performance), it sometimes appears to be a vendor competition to use the latest highest performing connectors at premium prices on the dev boards. This has the disadvantage of increasing the dev board cost and more importantly the peripheral or integration costs for anyone wishing to use the hardware inside their own projects.

Clearly something in between is needed, a mid density, easy to add into designs, low cost and hackable connection type. For BlackEdge I plan to use 1.27mm headers, these provide the density that is needed at low cost. They are also available as through hole and surface mount making them more accessible, one can also get hold of these from the common Asian outlets at low cost making them great for hacking etc..

The Physical part of the BlackEdge connectivity is pinout and form factor, so lets tackle that next. The planned form factor of the 'Core' Modules is 50mm x 50mm, this is a convenient size to integrate into a application specific hardware project of development carrier, it fits nicely into the common sizes offered at discounts by many of the Asian PCB suppliers making design and build accessible and low cost for all. The design also houses 4 * 2.5mm holes useful for optionally securing the 'Core' module to the base or carrier board using commonly available low cost standoffs, this adds physical security, important for things like robotics and tougher environments than the desktop..

The planned pinout on the 'Core' modules consist of two dual (25 each) row 50pin female connectors, these mate with similar male connectors on the base or carrier board. This enables the transport of the following signals:

• 4 CNTRL/CONF IO
• 7 Power Supply pins
• 9 JTAG/SWD/PROG
• Up to 16 Mixed signal IO lines
• Up to 64 Digital FPGA IO lines

Looking forward to your thoughts and feedback on the BlackEdge connectivity ideas..

[daveshah]

My understanding is that 1.27mm headers with sufficient grounding should be good for signals (including differential) up to at least 1Gbit/s - the ECP5 IO are limited to 800Mbit/s anyway. So electrical performance should not be a big issue.

If signal integrity becomes an issue, it can always be improved by setting some of the pins to outputs tied to 0 on the FPGA, and hard tieing those pins to actual ground on the carrier board (aka soft/virtual ground pins).

[Folknology]

My understanding is that 1.27mm headers with sufficient grounding should be good for signals (including differential) up to at least 1Gbit/s - the ECP5 IO are limited to 800Mbit/s anyway. So electrical performance should not be a big issue.

I think for most applications the signal bandwidth of the interconnect will be fine, BlackEdge isn't trying to providing maximum bandwidth via these connectors. An effort to keep the highest bandwidth connections on the 'Core' module is also being made in order to serve things like DDRRam and video for example.

If signal integrity becomes an issue, it can always be improved by setting some of the pins to outputs tied to 0 on the FPGA, and hard tieing those pins to actual ground on the carrier board (aka soft/virtual ground pins).

This is a good technique for squeezing extra signal bandwidth out of the connectivity albeit at the cost of extra IO..

[ken.boak]

Al,

How about a quick "sketch" in EagleCAD showing the proposed 50x50 pcb with connectors fitted.

It would be easier to see what you are proposing for the core board.

As FPGAs often offer a large number of GPIO, it would also be useful to use the other two edges of the board for future expansion.

[Folknology]

Ok some images to help visualise things better, here is an early Pmod carrier design I have been playing with:

And here is an entry level 'Core' module I am working on (female SMD headers on bottom):

This fits on top of the Pmod carrier, corresponding to dotted outline, hopefully that helps illustrate things a little better

[Folknology]

As FPGAs often offer a large number of GPIO, it would also be useful to use the other two edges of the board for future expansion.

Unfortunately the left edge on the entry level BlackEdge core board shown, is already populated. On the higher end versions both left and right edges are populated. However they are populated with really useful high speed connectors etc! Also it would be very difficult to escape the IOs if we used all sides for the interconnect!

[ken.boak]

Hi Al,

OK - I get a clearer picture.

I'm assuming that the HX4K 16Mb core is an upgraded derivative of BlackIce II - pretty much a self contained system with HDMI, USB, 16Mb RAM, config Flash, and an ARM included for assisting the config and providing ADC inputs. Is the 8 pin package a config flash or the reduced pinout CH340?

With more RAM and HDMI I expect that it would open up more SoC applications, including large screen instruments such as scopes and logic analysers. There may also be some interest from the retrocomputing community, looking for a platform with more memory and the potential for a more modern HDMI video display.

The GPIO is handled by SMT headers - which makes for a smaller footprint - and easier to integrate into projects on a carrier board - rather than ending up a s a "Christmas Tree" of PMODS - which is what the carrier board provides (upper picture) - should you want them.

So combining the two boards effectively gives a BlackIce II with 4 times the RAM and HDMI.

The one question I have is that if you are already placing SMT 1.27mm pin headers on the underside of the pcb - then it might make sense to place the RAM on the underside too - directly underneath the HX40K like BlackIce II. This would make for shorter more direct routing to the RAM and possibly a much easier route.

However, If you are proposing a 4 layer board - such as from PCBWay, a 50x50 4 layer board in 100+ quantities is about $1.30 less shipping.

It looks like an interesting new design

Ken

[Folknology]

I'm assuming that the HX40 16Mb core is an upgraded derivative of BlackIce II - pretty much a self contained system with HDMI, USB, 16Mb SRAM, config Flash, and an ARM included for assisting the config and providing ADC inputs. Is the 8 pin package a config flash or the reduced pinout CH340?

Yes that's right Ken and the 8 pin package is directly connected QSPI flash

With more SRAM and HDMI I expect that it would open up more SoC applications, including large screen instruments such as scopes and logic analysers. There may also be some interest from the retrocomputing community, looking for a platform with more memory and the potential for a more modern video display.

Yup that is spot on, Soc applications are definitely being targeted feature wise and having digital video output built in is a great bonus. On the entry level core this will have limited (retro?) resolution, but the higher end 'Core' modules can be pushed to 1020p at lower frame rates.

The GPIO is handled by SMT headers - which makes for a smaller footprint - and easier to integrate into projects on a carrier board - rather than ending up a s a "Christmas Tree" of PMODS - which is what the carrier board provides (upper picture) - should you want them.

Yup totally..

So combining the two boards effectively gives a BlackIce II with 4 times the RAM and HDMI.

And Flash and native USB2.0FS!

The one question I have is that if you are already placing SMT 1.27mm pin headers on the underside of the pcb - then it might make sense to place the RAM on the underside too - directly underneath the HX40K like BlackIce II. This would make for shorter more direct routing to the RAM and possibly a much easier route.

However, If you are proposing a 4 layer board - such as from PCBWay, a 50x50 4 layer board in 100+ quantities is about $1.30 less shipping.

I looked at both ways, this way turned out best and yup it's a 4 layer board. BTW the only SMD things on the underside are the female headers and SDCard holder which are often hand finished, although a 2nd P&P pass might work.

Thanks ken..