Beginners question on how to use (PLL) clock on Ice40

[DoctorZ]

Hi there,

Let me first say, that i'm a complete beginner with FPGA. I am a software programmer with some hobby knowledge about analog electronics, so forgive any noob questions. I completely new in digital / FPGA wonderland.

Having that said.. i have created a simple logic circuit with IceStudio. That I want to trigger on 250 Hz. if I understand correctly the Ice40 has an internal clock of 25MHz which I can use? Seems to me that I need to divide it by a factor of 1000.

So I hooked up my digital scope to P31/9 of MX1 of the BlackIce MX. Somehow I found out using this file:
https://raw.githubusercontent.com/FPGAwars/icestudio/develop/app/resources/boards/blackice-mx/pinout.json
that this pin maps to a label called "PMOD[15]" in Icestudio. Which I still find strange and don't understand:

But that a side, whenever I set this output high or low within the FPGA logic I see the result on the scope. So it seems to work. Now I created a basic connection from the input "CLK" to my Testpin output, like this:

And I would have expected to see a 25 MHz signal on my scope. Which It doesn't, instead it indicates a 1.858 KHz signal.

So what am I overseeing here? I understand that this is forum is probably not the most optimal place for this kind of generic FPGA beginners questions. But i'm still finding my way around, I hope you guys have some tips to put me in the right direction.

Kind regards,

Bastiaan

Update:

I found out that my scope only goes up to 20MHz. So the clock signal was probably fast to capture. I have placed a Prescalar block with a value of 16 in between the CLK and TESTPIN.

Now i'm seeing a frequency of 381Hz on the scope, which is too fast for my logic,, but already in the right direction. Still I am unable to find a way to get it exactly on 250 Hz. Because when I change the value of 16 to 17. The frequency ends up around 190Hz which is too low for my application. Any suggestions?

[lawrie]

That I want to trigger on 250 Hz. if I understand correctly the Ice40 has an internal clock of 25MHz which I can use? Seems to me that I need to divide it by a factor of 1000.

You need to divide by 100,000 to get from 25000000 to 250.

Because when I change the value of 16 to 17. The frequency ends up around 190Hz which is too low for my application. Any suggestions?

The icestudio prescaler divides by a power of 2. So 16 divides by 65536 and 17 by 131072. You want to divide by 100000.

I don't know if icestudio has a block that does that. You will probably have to write you a Verilog code block, with something like:

reg [15:0] pre_scaler = 0;
reg clk_out = 0;

always @(posedge clk_in) begin
  if (pre_scaler == 50000 - 1) begin
    pre_scaler <= 0;
    clk_out <= ~clk_out;
  end
end

What you are using is a pre-scaler or clock divider, not a PLL. To use a PLL you can to use an SB_PLL40_CORE instance. I don't know if icestudio provides a way to create a pll. A PLL won't directly do what you want as it cannot produce a clock anywhere like that slow, but it might be able to produce a clock that you could divide by a power of 2, to get what you want.