Yes, I believe what David Banks meant was that when a request is made from a clock running at 32MHz, the data must be available on the next clock cycle.
The Mist/Mister SDRAM implementation can do a read in exactly 8 clock cycles of the sdram clock, so that needs to be 8 times as fast as the clock that makes the request.
Now that David has reduced the requirement of the clock that makes the request to 8MHz, an sdram clock of 64MHz could be used, which I have successfully used on a Blackice Mx board.