There are several levels of BlackIce developers:
1) IceStudio - easiest way in
2) APIO + Editor, simple for getting started especially for Windows.
3) Socs using Litex/Saxon etc..
4) Verilog, make, command line and editor
Trouble is for the last category there are many ways to work, the example make file in blink is the simplest example. It is based on Arachne PNR and the iceStorm tools, which have been around longest, it's a lowest common denominator. In reality you would probably want to move to using NextPnr. In addition how will you run test benches and simulation, will you use Icarus or prefer co-simulation with Verilator? These kind of differences will change how you structure you make file, here is a simple example I used recently for a 7Seg demo:
VERILOG = top.v hex27seg.v 7seg_display.v
LDFLAGS=
CFLAGS=-g -O3
chip.bin: $(VERILOG) 7seg_display.pcf
# yosys -q -p "synth_ice40 -blif top.blif" $(VERILOG)
# arachne-pnr -d 8k -P tq144:4k -p 7seg_display.pcf top.blif -o top.txt
yosys -q -p "synth_ice40 -json top.json" $(VERILOG)
nextpnr-ice40 --hx8k --package tq144:4k --pcf 7seg_display.pcf --json top.json --asc top.txt
icepack top.txt top.bin
.PHONY: sim
sim:
verilator -Wno-fatal --cc $(VERILOG) --trace --exe ../$(@).cpp -Mdir $(@) -CFLAGS "$(CFLAGS)"
make -C $(@) -f Vtop.mk
.PHONY: upload
upload:
stty -F /dev/ttyS3 raw -echo
cat top.bin >/dev/ttyS3
.PHONY: clean
clean:
$(RM) -f top.blif top.json top.txt top.ex .bin
$(RM) -rf *.o
distclean:: clean
rm -rf *~ *.txt *.vcd *.mif *.orig
I haven't even touched on adding more advanced features in Yosys like Formal support. Automating all of this would be difficult because folks operate in many different ways..
