This looked interesting: a high level frontend for FPGA tools, whereby you do your system-level design in python, using IP as needed from a supplied library, and also including any verilog blocks you have designed. That is, it's slightly upstream from HDL, for better productivity (but more flexible and more abstract than MyHDL.)
See Bunnie Huang's blog post here:
where he says it's a big win compared to Xilinx' tools (IceStorm is also supported, for Lattice):
LiteX produces a design that uses about 20% of an XC7A50 FPGA with a runtime of about 10 minutes, whereas Vivado produces a design that consumes 85% of the same FPGA with a runtime of about 30-45 minutes.
LiteX is a soft-fork of Migen/MiSoC – a python-based framework for managing hardware IP and auto-generating HDL. The IP blocks within LiteX are completely open source, and so can be targeted across multiple FPGA architectures. However, for low-level synthesis, place & route, and bitstream generation, it still relies upon proprietary chip-specific vendor tools, such as Vivado when targeting Artix FPGAs. It’s a little bit like an open source C compiler that spits out assembly, so it still requires vendor-specific assemblers, linkers, and binutils.
There's a number of links at the bottom of the blog post. The Migen manual is here:
As a caveat:
My final thought is that LiteX, in its current state, is probably best suited for people trained to write software who want to design hardware, rather than for people classically trained in circuit design who want a tool upgrade. The design idioms and intuitions built into LiteX pulls strongly from the practices of software designers